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Somayyeh Timarchi

Associate Professor

Update: 2024-05-15

Somayyeh Timarchi

Electrical Engineering - Electronics and Telecommunications /

Journal Papers

  1. "Non-Volatile and High-Performance Cascadable Spintronic Full-Adder with no Sensitivity to Input Scheduling"
    Mina Raouf, Somayyeh Timarchi
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, Vol. 70, pp.2236-2240, 2023
  2. "Two Efficient Approximate Unsigned Multipliers by Developing New Configuration for Approximate 4:2 Compressors"
    Ladan Sayadi, Somayyeh Timarchi, Akbar Sheikh-Akbari
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, Vol. 70, pp.1649-1659, 2023
  3. "Reducing the Effect of Carry Propagation on Spintronic Adders"
    Mina Raouf, Somayyeh Timarchi
    SPIN, Vol. 12, 2022
  4. "Ultra-lightweight FPGA-based RC5 designs via data-dependent rotation block optimization"
    Yahya Arzani birgani, Somayyeh Timarchi, Ayesha Khalid
    MICROPROCESSORS AND MICROSYSTEMS, Vol. 93, 2022
  5. "Teaching redundant residue number system for electronics and computer students"
    Somayyeh Timarchi
    International Journal of Mathematical Education in Science and Technology, Vol. -, pp.1-19, 2022
  6. "Area-Time-Efficient Scalable Schoolbook Polynomial Multiplier for Lattice-Based Cryptography"
    Yahya Arzani birgani, Somayyeh Timarchi, Ayesha Khalid
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, Vol. 69, pp.5079-5083, 2022
  7. "Efficient Approximate Multiplier Based on a New 1-Gate Approximate Compressor"
    Seyed Amir Hossein Ejtahed, Somayyeh Timarchi
    CIRCUITS SYSTEMS AND SIGNAL PROCESSING, Vol. 41, pp.2699-2718, 2022
  8. "Sign Detection and Signed Integer Comparison for the 3-Moduli Set {2^n-1,2^(n+k),2^n+1}?"
    Zeinab Torabi, Somayyeh Timarchi
    Computer Science, Vol. 22, pp.387-401, 2021
  9. "Area and Power-Efficient Variable-Sized DCT Architecture for HEVC Using Muxed-MCM Problem"
    Ahmad Shabani, Mohammad Sabri, Bahareh Khabbazan, Somayyeh Timarchi
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, Vol. 68, pp.1259-1268, 2021
  10. "Improved Distributed Particle Filter Architecture with Novel Resampling Algorithm for Signal Tracking"
    Zahra Talebi, Somayyeh Timarchi
    International Journal of Engineering, Vol. 33, pp.2482-2488, 2020
  11. "Improving Architectures of Binary Signed-Digit CORDIC With Generic/Specific Initial Angles"
    Hossein Mahdavi, Somayyeh Timarchi
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, Vol. 67, pp.2297-2304, 2020
  12. "Efficient Error Detection and Correction Method for 1-out-of-3 Binary Signed Digit Adders"
    Adib Armand, Somayyeh Timarchi
    INTERNATIONAL JOURNAL OF ELECTRONICS, Vol. 106, pp.1427-1440, 2019
  13. "Area-Time-Power Efficient Maximally Redundant Signed-Digit Modulo 2n ? 1 Adder and Multiplier"
    Somayyeh Timarchi, Negar Akbarzadeh Chini Foroush
    CIRCUITS SYSTEMS AND SIGNAL PROCESSING, Vol. 38, pp.2138-2164, 2019
  14. "Area-Time-Power Efficient FFT Architectures Based on Binary-Signed-Digit CORDIC"
    Hossein Mahdavi, Somayyeh Timarchi
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, Vol. 66, pp.3874-3881, 2019
  15. "Power and area efficient CORDIC-Based DCT using direct realization of decomposed matrix"
    Ahmad Shabani, Somayyeh Timarchi, Hossein Mahdavi
    MICROELECTRONICS JOURNAL, Vol. 91, pp.11-21, 2019
  16. "Optimized Parity-Based Error Detection and Correction Methods for Residue Number System"
    Adib Armand, Somayyeh Timarchi, Hossein Mahdavi
    JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS, Vol. 28, 2019
  17. "Low-Power and Fast Full Adder by Exploring New XOR and XNOR Gates"
    Hamed Naseri, Somayyeh Timarchi
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, Vol. 26, pp.1481-1493, 2018
  18. "Low-Power DCT-Based Compressor for Wireless Capsule Endoscopy"
    Ahmad Shabani, Somayyeh Timarchi
    SIGNAL PROCESSING-IMAGE COMMUNICATION, Vol. 59, pp.83-95, 2017
  19. "Efficient modulo 2n 1 multiplier"
    Masoud Abbasi Alaie, Somayyeh Timarchi
    International Journal of Computer Aided Engineering and Technology, Vol. 8, pp.260-276, 2016
  20. "An Ultra-Low-Power 9T SRAM Cell Based on Threshold Voltage Techniques"
    Majid Moghaddam, Somayyeh Timarchi, Mohammad Hossein Moaiyeri, Mohammad Eshghi
    CIRCUITS SYSTEMS AND SIGNAL PROCESSING, Vol. 35, pp.1437-1455, 2016
  21. "Fast Architecture for Decimal Digit Multiplier"
    Mahmood Fazlali, Hadi Valikhani, Somayyeh Timarchi, Hadi Tabatabaee Malazi
    MICROPROCESSORS AND MICROSYSTEMS, Vol. 39, pp.296-301, 2015
  22. "Generalized Fault-Tolerant Stored-Unibit-Transfer RNS Multiplier for Moduli Set 2n-1 2n 2n 1"
    Somayyeh Timarchi, Mahmood Fazlali
    IET Computers and Digital Techniques, Vol. 6, pp.269-276, 2012
  23. "Efficient Modular Binary Signed-Digit Multiplier for the moduli set 2n-1 2n 2n 1"
    Maryam Saremi, Somayyeh Timarchi
    Journal on Computer Science and Engineering, Vol. 9, pp.52-62, 2011
  24. "Efficient Reverse Converter Designs for the New 4-Moduli Sets 2n 1 2n 2n 1 22n 1 1 and 2n 1 2n 1 22n 22n 1 Based on New CRTs"
    , Keyvan Navi, , , Somayyeh Timarchi
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, Vol. 57, pp.823-835, 2010
  25. "A novel low-power full-adder cell for low voltage"
    Keyvan Navi, Mehrdad Maeen, Vahid Foroutan, Somayyeh Timarchi, Omid Kavehei
    INTEGRATION-THE VLSI JOURNAL, Vol. 42, pp.457-467, 2009
  26. "Arithmetic Circuits of Redundant SUT-RNS"
    Somayyeh Timarchi, Keyvan Navi
    IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, Vol. 58, pp.2959-2968, 2009
  27. "Improved Modulo 2n +1 Adder Design"
    Somayyeh Timarchi, Keyvan Navi
    International journal of computer and information science and engineerin, Vol. 2, pp.158-165, 2008
  28. "Modulo 2n+1 Multiplication and Multiply-Accumulate Units for Digital Signal Processor"
    Negar Akbarzadeh Chini Foroush, Somayyeh Timarchi
    Vol. 35, pp.127-138, 2018

Conference Papers

  1. ""
    Mohammad ebrahim Romani, Somayyeh Timarchi
    27th Iranian Conference on Electrical Engineering ICEE2019, 2019
  2. "Novel Algorithm and Architectures for High-Speed Low-Power ConText-Based Steganography"
    Somayyeh Timarchi, Masoud Abbasi Alaie, Hosein Kooshkbaghi
    19th CSI International Symposium on Computer Architecture and Digital Systems (CADS17), 2017
  3. "Ultra-Low Voltage Standard Cell Libraries Design Strategies and a Case Study"
    Somayyeh Timarchi, Massimo Alioto
    The 23rd IEEE International Conference on Electronics Circuits and Systems (ICECS), pp.520-523, 2016
  4. ""
    Amir Abbas Hamidi Imani, Somayyeh Timarchi, Negar Akbarzadeh Chini Foroush
    1st International Conference on New Research Achievements in Electrical and Computer Engineering, 2016
  5. "Block-based hardware implementation of FAST corner detection algorithm"
    Amir Abbas Hamidi Imani, Somayyeh Timarchi, Negar Akbarzadeh Chini Foroush
    1st International Conference on New Research Achievements in Electrical and Computer Engineering, 2016
  6. "Maximally Redundant High-Radix Signed-Digit Residue Number System"
    Somayyeh Timarchi, Negar Akbarzadeh Chini Foroush, Amir Abbas Hamidi Imani
    18th CSI International Symposium on Computer Architecture Digital Systems (CADS 2015), 2015
  7. "High-speed energy-efficient 5 2 compressor"
    Ardalan Najafi, Somayyeh Timarchi, amir najafi
    37th International Convention on information and communication technology electronics and microelectronics, pp.80-84, 2014
  8. "Efficient 1-out-of-3 Binary Signed-Digit Multiplier for the moduli set 2n-1 2n 2n 1"
    Maryam Saremi, Somayyeh Timarchi
    17th CSI International symposium on Computer Architecture and Digital Systems (CADS2013), pp.123-124, 2013
  9. "High-speed binary signed-digit RNS adder with posibit and negabit encoding"
    Somayyeh Timarchi, Maryam Saremi, Mahmood Fazlali, Georgi Gaydadjiev
    21st IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), pp.58-59, 2013
  10. "Efficient Class of Redundant Residue Number System"
    Somayyeh Timarchi
    ISVLSI 2013, pp.10-16, 2013
  11. "1-out-of-3 Binary Signed-Digit Modular Adder"
    Maryam Saremi, Somayyeh Timarchi
    5-th conference on Information Knowledge Technology (IKT), 2013
  12. "A Novel High-Speed Low-Power Binary Signed-Digit Adder"
    Somayyeh Timarchi, Parham Ghayoor,
    16th CSI International Symposium on Computer Architecture and Digital System, pp.70-74, 2012
  13. "A unified addition structure for moduli set 2n-1 2n 2n 1 based on a novel RNS representation"
    Somayyeh Timarchi, Mahmood Fazlali, Sorin D.Cotofana
    28th IEEE International Conference on Computer Design (ICCD 2010), pp.247-252, 2010
  14. "An Efficient Power-Area-Delay Modulo 2n-1 Multiplier"
    Somayyeh Timarchi, Mahmood Fazlali
    the 15th CSI international symposium on computer architecture and digital systems (cads), pp.157-160, 2010
  15. "Maximally Redundant High-Radix Signed-Digit Adder New Algorithm and Implementation"
    Somayyeh Timarchi, Keyvan Navi, Omid Kavehei
    IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2009), pp.97-102, 2009
  16. "Efficient Class of Redundant Residue Number"
    Somayyeh Timarchi, Keyvan Navi
    2007 IEEE International Symposium on Intelligent Signal Processing, pp.1-6, 2007
  17. "EVALUATION OF SOME EXPONENTIAL RANDOM NUMBER GENERATORS IMPLEMENTED BY FPGA"
    Somayyeh Timarchi, S. Ghassem Miremadi, Alireza Ejlali
    The IASTED International Conference on Parallel and Distributed Computing and Networks (PDCN 2005), pp.578-583, 2005
  18. "Design and Implementation of a Low-Power FIR Filter"
    Ali Dehghani Firouzabadi, Somayyeh Timarchi, Kiavash Ghamsari
    The 2nd Iranian Conference on Microelectronics (ICM2020), 2020
  19. ""
    Ladan Sayadi, Somayyeh Timarchi
    28th Iranian Conference on Electrical Engineering (ICEE 2020), pp.1-5, 2020
  20. "Power Investigation of 4-2 Compressors by Changing Input Switching Activity"
    Amir mohammad Ketabchi, Somayyeh Timarchi
    The 1st Iranian Conference on Microelectronics, pp.1-4, 2019
  21. ""
    Yahya Arzani Birgani, Somayyeh Timarchi
    9th National Conference on Command Control Communication and Computers Intelligence (C4I), 2016
  22. ""
    Yahya Arzani Birgani, Somayyeh Timarchi
    13th International ISC Conference on Information Security and Cryptology (ISCISC 2016), 2016
  23. "Low Power Design of Binary Signed Digit Residue Number System Adder"
    Adib Armand, Somayyeh Timarchi
    ICEE 2016, 2016
  24. "Efficient Multiply-add Unit Specified for DSPs Utilizing Low-Power Pipeline Modulo 2n 1 Multiplier"
    Negar Akbarzadeh Chini Foroush, Somayyeh Timarchi, Amir Abbas Hamidi Imani
    , 2015
  25. ""
    Ahmad Shabani, Somayyeh Timarchi
    , 2015
  26. ""
    Ardavan Yazdi, Somayyeh Timarchi
    I, pp.3465-3470, 2014
  27. ""
    Masoud Abbasi Alaie, Somayyeh Timarchi
    I, pp.2563-2568, 2014
  28. "Radix-4 Implementation of Redundant Interleaved Modular Multiplication on FPGA"
    Loghman Rahimzadeh, Mohammad Eshghi, Somayyeh Timarchi
    I, pp.523-526, 2014
  29. "A Novel Modulo 2n+1 Adder Scheme"
    Somayyeh Timarchi, Keyvan Navi
    12th Annual International CSI Computer Conference (CSICC 2007), 2007
  30. ""
    Mehdi Hosseinzade, Somayyeh Timarchi, Amir Pasha Mirbaha, Keyvan Navi
    14th Iranian Conference on Electrical Engineering ICEE2006, 2006
  31. ""
    Somayyeh Timarchi, Keyvan Navi, Mehdi Hosseinzadeh
    11th Annual International CSI Computer Conference (CSICC 2006), 2006
  32. ""
    Somayyeh Timarchi, Keyvan Navi
    11th Annual International CSI Computer Conference (CSICC 2006), 2006
  33. "A Comparative Evaluation of Some Hardware-Based Pseudo-Random Number Generators"
    Somayyeh Timarchi, S. Ghassem Miremadi, Alireza Ejlali
    10th Annual CSI Computer Conference (CSICC 2005), pp.17-25, 2005